Process placement in a processor array
US8352955B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Feb 10, 2009 |
| Grant date | Jan 8, 2013 |
| Priority date | — |
| Expiry date | Oct 6, 2031 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/5066
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
There is provided a method for placing a plurality of processes onto respective processor elements in a processor array, the method comprising (i) assigning each of the plurality of processes to a respective processor element to generate a first placement; (ii) evaluating a cost function for the first placement to determine an initial value for the cost function, the result of the evaluation of the cost function indicating the suitability of a placement, wherein the cost function comprises a bandwidth utilization of a bus interconnecting the processor elements in the processor array; (iii) reassigning one or more of the processes to respective different ones of the processor elements to generate a second placement; (iv) evaluating the cost function for the second placement to determine a modified value for the cost function; and (v) accepting or rejecting the reassignments of the one or more processes based on a comparison between the modified value and the initial value.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.