Semiconductor device wherein a property of a first semiconductor layer is different from a property of a second semiconductor layer

US8354674B2 · kind B2 · utility

Assignee

• Semiconductor Energy Laboratory Co., Ltd. · JP

Inventor

• Hajime Kimura · Yokohama, JP

Key dates

• Filing date: Jun 13, 2008
• Grant date: Jan 15, 2013
• Expiry date: May 11, 2029

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D86/471

Abstract

It is an object to provide a semiconductor device which has a large size and operates at high speed. A top gate transistor which includes a semiconductor layer of single-crystal and a bottom gate transistor which includes a semiconductor layer of amorphous silicon (microcrystalline silicon) are formed over the same substrate. Then, gate electrodes of each transistor are formed with the same layer, and source and drain electrodes are also formed with the same layer. Thus, manufacturing steps are reduced. In other words, two types of transistors can be manufactured by adding only a few steps to the manufacturing process of a bottom gate transistor.