Resistance change memory
US8355275B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 22, 2011 |
| Grant date | Jan 15, 2013 |
| Priority date | — |
| Expiry date | Sep 22, 2031 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2213/76
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
According to one embodiment, a resistance change memory includes a memory cell including a resistance change element and a stacked layer structure which are connected in series, a control circuit configured to control a first operation of changing the resistance change element from a first resistance value to a second resistance value lower than the first resistance value, and a voltage pulse generating circuit configured to generate a first voltage pulse to be applied to the memory cell in the first operation. The stacked layer structure includes two conductive layers and an insulating layer formed between the two conductive layers. Amplitude of the first voltage pulse is in a first voltage area in which the stacked layer structure functions as a capacitor. The first voltage pulse satisfies Ron×C<T-lead<Roff×C and Ron×C<T-trail.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.