Memory device, semiconductor memory device and control method thereof
US8355289B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 24, 2009 |
| Grant date | Jan 15, 2013 |
| Priority date | — |
| Expiry date | Dec 30, 2029 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/4097
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor memory device comprises a memory cell array, first and second bit lines, first and second amplifiers, and a sense amplifier control circuit. An amplifying element in the first sense amplifier amplifiers the signal of the first bit line and converts it into an output current. The second bit line is selectively connected to the first bit line via the first sense amplifier. A signal voltage decision unit in the second sense amplifier determines the signal level of the second bit line being supplied with the output current. The sense amplifier control circuit controls connection between the amplifying element and the unit in accordance with a determination timing, which switches the above connection from a connected state to a disconnected state at a first timing in a normal operation and switches in the same manner at a delayed second timing in a refresh operation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.