Delay time measurement apparatus, storage medium storing delay time measurement program and network system
US8355341B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 23, 2010 |
| Grant date | Jan 15, 2013 |
| Priority date | — |
| Expiry date | Jul 20, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L43/0852
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A CPU executes a process including determining a core node among plural relay nodes on a basis of route information, acquiring a first and a second packets flowing between a server and a terminal apparatus, the second packet being transmitted on a basis of the first packet, calculating a first delay time on a basis of the first and the second packets, the first delay time relating to packet transmission between the server and the terminal apparatus, transmitting a third packet to the core node, receiving a response to the third packet from the core node, calculating a second delay time on a basis of the third packet and the response, the second delay time being a delay time of the core node, and calculating a third delay time being a delay time of an end node on a basis of the first and the second delay times.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.