Memory device and control method
US8356135B2 · kind B2 · utility
1Cited by
2References
13Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | May 22, 2009 |
| Grant date | Jan 15, 2013 |
| Priority date | — |
| Expiry date | Dec 14, 2030 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/7201
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory device includes a first controller and a second controller. The first controller receives a first command from a host and stores the first command in a first command queue, and transmits the first command to the second controller relating to the first command stored in the first command queue. The second controller transmits the first command stored in the second command queue to a flash memory.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.