Decryption system and method for reducing processing latency of stored, encrypted instructions
US8356186B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Oct 1, 2009 |
| Grant date | Jan 15, 2013 |
| Priority date | — |
| Expiry date | Apr 17, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L9/0894
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A present novel and non-trivial decryption system and methods are disclosed for reducing latency associated with the decryption and execution of stored, encrypted instructions. The system comprises a storage device, a processor, a controller, a key generator, a plurality of memory banks, a plurality of bus switches, and a combiner. Upon receiving a processor command, the controller changes the switch positions of a plurality of switches, where a first switch is operatively coupled to a key generator, a second switch to a combiner for performing a combinatory decryption process, and both switches to plurality of memory banks. When a partition is switched, the processor executes data of an instruction immediately upon completion of the combinatory decryption process using at least one character retrieved from one memory bank while the next decryption key is generated and loaded into another memory bank at the same time.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.