Yield based flop hold time and setup time definition
US8356263B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 30, 2011 |
| Grant date | Jan 15, 2013 |
| Priority date | — |
| Expiry date | Jun 30, 2031 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2119/12
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Systems and method for defining a timing parameter for a circuit element based on process variation, including, determining a point of failure parameter associated with the timing parameter, the point of failure parameter correlated with a specific value of the process variation. A standard deviation associated with the point of failure parameter is determined. The process variation per the standard deviation is calculated and the timing parameter for the circuit element is defined as a function of the failure parameter, the standard deviation, and the process variation per the standard deviation. A margin factor, which varies with the standard deviation, is optionally applied to the timing parameter. The timing parameter may be one of a setup time or hold time.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.