Implementing enhanced clock tree distributions to decouple across N-level hierarchical entities
US8356264B2 · kind B2 · utility
4Cited by
13References
20Claims
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Key dates
| Filing date | Oct 28, 2010 |
| Grant date | Jan 15, 2013 |
| Priority date | — |
| Expiry date | Mar 16, 2031 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/398
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method, system and computer program product for implementing enhanced clock tree distributions to decouple across N-level hierarchical entities of an integrated circuit chip. Local clock tree distributions are constructed. Top clock tree distributions are constructed. Then constructing and routing a top clock tree is provided. The local clock tree distributions and the top clock tree distributions are independently constructed, each using an equivalent local clock distribution of high performance buffers to balance the clock block regions.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.