Display substrate and method of manufacturing the same
US8357554B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 9, 2011 |
| Grant date | Jan 22, 2013 |
| Priority date | — |
| Expiry date | Jul 15, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D86/423
Abstract
A display substrate having a low resistance signal line and a method of manufacturing the display substrate are provided. The display substrate includes an insulation substrate, a gate line, a data line and a pixel electrode. The gate line gate line is formed through a sub-trench and an opening portion. The sub-trench is formed in the insulation substrate and the opening portion is formed through a planarization layer on the insulation substrate at a position corresponding to the position of the sub-trench. The data line crosses the gate line. The pixel electrode is electrically connected to the gate line and the data line through a switching element. Thus, a signal line is formed through a trench formed by using a planarization layer and an insulation substrate, so that a resistance of the signal line may be reduced.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.