Methods of fabricating semiconductor memory devices
US8357605B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 25, 2011 |
| Grant date | Jan 22, 2013 |
| Priority date | — |
| Expiry date | Jul 25, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/7682
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Methods of forming memory devices are provided. The methods may include forming a pre-stacked gate structure including a lower structure and a first polysilicon pattern on the substrate. The methods may also include forming an insulation layer covering the pre-stacked gate structure. The methods may further include forming a trench in the insulation layer by removing a portion of the first polysilicon pattern. The methods may additionally include forming a metal film pattern in the trench on the first polysilicon pattern. The methods may also include forming a first metal silicide pattern by performing a first thermal treatment on the first polysilicon pattern and the metal film pattern. The methods may further include forming a second polysilicon pattern in the trench. The methods may additionally include forming a second metal silicide pattern by performing a second thermal treatment on the second polysilicon pattern and the first metal silicide pattern.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.