High speed orthogonal gate EDMOS device and fabrication

US8357986B2 · kind B2 · utility

Assignee

• Asahi Kasei Microdevices Corporation · JP

Inventors

• Hao Wang · Shanghai, CN
• Wai Tung Ng · Plano, US
• Huaping Xu · 流花街道, CN

Key dates

• Filing date: May 15, 2009
• Grant date: Jan 22, 2013
• Expiry date: Aug 24, 2029

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D64/513

Abstract

An orthogonal gate extended drain MOSFET (EDMOS) structure provides a low gate-to-drain capacitance (CGD) and exhibits increased reliability. It has a gate electrode that is folded into the shallow trench isolation (STI) oxide region. Horizontal and vertical gate electrode segments provide gate control. It accommodates both high voltage devices and standard CMOS components on the same substrate. Reduced surface field (RESURF) technology is employed to optimize tradeoffs between high breakdown voltage and specific on-resistance. Device fabrication steps are compatible with standard CMOS flow and process modules can be added or removed from baseline CMOS technology.