Multi-level nonvolatile memory devices using variable resistive elements
US8358527B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 16, 2010 |
| Grant date | Jan 22, 2013 |
| Priority date | — |
| Expiry date | Mar 12, 2031 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2213/72
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Multi-level nonvolatile memory devices using variable resistive elements, the multi-level nonvolatile memory devices including a word line, a bit line, and a multi-level memory cell coupled between the word line and the bit line, the multi-level memory cell having first resistance level and a second resistance level higher than the first resistance level when the first and second write biases having the same polarity are applied thereto, and a third resistance level and a fourth resistance level ranging between the first and second resistance levels, when third and fourth write biases having different polarities from each other are applied thereto.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.