Interface between chip rate processing and bit rate processing in wireless downlink receiver
US8358988B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 28, 2006 |
| Grant date | Jan 22, 2013 |
| Priority date | — |
| Expiry date | May 15, 2029 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04B2201/70707
- WIPO fieldTelecommunications
- WIPO sectorElectrical engineering
Abstract
A bit rate processor in a wireless system includes a front end processor to process physical channel data and to generate encoded transport channel data, a transport channel buffer to hold the encoded transport channel data, and a back end processor to process the encoded transport channel data from the transport channel buffer and to generate decoded transport channel bits. The front end process may include a frame buffer that receives the physical channel data, a first stage to de-map the physical channel data, an intermediate frame buffer that receives the de-mapped physical channel data, and a second stage to process the de-mapped physical channel data and to provide the encoded transport channel data. The back end processor may include a third stage, including a scaling circuit to scale the encoded transport channel data, a decoder to decode the scaled transport channel data, a CRC checker and an output buffer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.