Semiconductor device
US8359427B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | May 28, 2010 |
| Grant date | Jan 22, 2013 |
| Priority date | — |
| Expiry date | May 20, 2031 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/455
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In executing an EEPROM emulation by a flash memory incorporated in a semiconductor device, there is a problem that the data holding period of the flash memory is shorter than the EEPROM. The flash memory manages data by block unit. Therefore, it is required to securely perform a block change before the specification of the data holding period of the flash memory passes. For satisfying this problem, for an EEPROM substitution area in a flash memory, a data level check voltage is set between an internal verification voltage and a read-out voltage. When data level becomes below the data level check voltage, the block change is performed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.