Memory banking system and method to increase memory bandwidth via parallel read and write operations
US8359438B2 · kind B2 · utility
1Cited by
3References
15Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | May 18, 2010 |
| Grant date | Jan 22, 2013 |
| Priority date | — |
| Expiry date | May 20, 2031 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0844
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A cache memory and a tag memory are included in a banked memory system and used to effectively enable parallel write and read operations on each clock cycle, even though the memory banks consist of single-port devices that are not inherently capable of parallel write and read operations.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.