Patent · US Active

Method and system for generating an integrated circuit chip facility waveform from a series of chip snapshots

US8359503B2 · kind B2 · utility

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0References

24Claims

0Family size

Assignee

International Business Machines Corporation · US

Inventors

Rolf Fritz · Waldenbuch, DE
Andreas C. Koenig · Rockford, US
Christopher Smith · Rochester, US
Manfred Walz · Pfalzgrafenweiler, DE

Key dates

Filing date	Sep 16, 2008
Grant date	Jan 22, 2013
Priority date	—
Expiry date	Nov 23, 2031

Classification

Technology area (CPC G)Physics
CPC primaryG01R31/31707
WIPO fieldMeasurement
WIPO sectorInstruments

Abstract

Methods and corresponding test systems for generating a chip facility waveform from a series of chip snapshots. The methods including, (i) testing an integrated chip multiple times, each time increasing a clockstop delay delaying a clockstop generated by triggered error condition each time determining the state of state holding elements of the integrated circuit and (ii) testing an integrated circuit chip one time to generate a error condition and determining multiple times the states of state holding elements of the integrated circuit based on previous states of the state holding elements.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.