Power semiconductor device having adjustable output capacitance
US8362529B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 21, 2010 |
| Grant date | Jan 29, 2013 |
| Priority date | — |
| Expiry date | Jun 24, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/146
Abstract
A power semiconductor device having adjustable output capacitance includes a semiconductor substrate having a first device region and a second device region defined thereon, at lest one power transistor device disposed in the first device region, a heavily doped region disposed in the semiconductor substrate of the second device region, a capacitor dielectric layer disposed on the heavily doped region, a source metal layer disposed on a top surface of the semiconductor substrate and electrically connected to the power transistor device, and a drain metal layer disposed on a bottom surface of the semiconductor substrate. The source metal layer in the second device, the capacitor dielectric layer and the heavily doped region form a snubber capacitor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.