Mode latching buffer circuit
US8362803B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 18, 2011 |
| Grant date | Jan 29, 2013 |
| Priority date | — |
| Expiry date | Feb 18, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K3/356182
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A voltage translator circuit includes an input stage adapted for receiving an input signal referenced to a first voltage supply, a first latch circuit adapted for connection with a second voltage supply and operative to at least temporarily store a logic state of the input signal, and a voltage clamp coupled between the input stage and the first latch circuit. The voltage clamp is operative to set a maximum voltage across the input stage to a prescribed level. The voltage translator circuit generates a first output signal at a first output formed at a junction between the first latch circuit and the voltage clamp. A second latch circuit is connected to the first output in a feedback configuration. The second latch circuit is operative to retain a logical state of the first output signal as a function of at least a first control signal supplied to the second latch circuit regardless of a state of the first voltage supply.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.