Power switch ramp rate control using daisy-chained flops
US8362805B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 15, 2010 |
| Grant date | Jan 29, 2013 |
| Priority date | — |
| Expiry date | Jun 24, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/0016
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
In an embodiment, an integrated circuit may include one or more power managed blocks and a power manager circuit. The power manager circuit may be configured to generate a block enable for each power managed block and a block enable clock. The power managed block may generate local block enables to various power switches in the power managed block, staggering the block enables over two or more block enable clock cycles. In particular, the power managed block may include a set of series-connected flops that receive the block enable from the power manager circuit. The output of each flop may be coupled to a respective set of power switches and may enabled those switches. The change in current flow due to enabling and/or disabling the power managed block may thus be controlled. In an embodiment, the frequency of the block enable clock may be set to a defined value independent of process, voltage, and temperature conditions in the integrated circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.