Sampling filter using multiple clocks
US8362828B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 14, 2008 |
| Grant date | Jan 29, 2013 |
| Priority date | — |
| Expiry date | Apr 27, 2029 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03H15/00
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Methods and devices for forming a series of samples of a filtered version of an input signal. Multiple tap current cells each generate a tap current from the signal. Multiple distribution means couple the tap current cells with multiple integrating means. The distribution means is controlled by a first clock signal. The multiple integrating means integrate tap currents that they receive and these integrating means form the samples. The tap currents generated are each sent to each integrating means in a predetermined sequence according to the first clock signal. The integrating means each use integrating and sampling phases controlled by a second clock signal. During the integrating phase an integrating means receives tap currents in sequence, while during the rest phase, no tap currents are received and the contents of the circuit are sampled and the integrator means is reset.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.