Delay line that tracks setup time of a latching element over PVT
US8363485B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 15, 2009 |
| Grant date | Jan 29, 2013 |
| Priority date | — |
| Expiry date | Feb 11, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K3/356156
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A latching element latches incoming data into an integrated circuit. The latching element (for example, a latch or flip-flop) can be considered to include a data path portion, a clock path portion, and an ideal latching element. In one embodiment, an open-loop replica of the data path portion is disposed in a clock signal path between a clock input terminal of the integrated circuit and a clock input lead of the latching element. In a second embodiment, an additional replica of the clock path portion is disposed in a data signal path between a data terminal of the integrated circuit and a data input lead of the latching element. The replica circuits help prevent changes in skew between a data path propagation time to the ideal latching element and clock path propagation time to the ideal latching element. Setup times remain substantially constant over PVT (process, supply voltage, temperature).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.