System and method for correcting programming failures in a programmable fuse array
US8363502B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Nov 19, 2010 |
| Grant date | Jan 29, 2013 |
| Priority date | — |
| Expiry date | May 27, 2031 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C17/18
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system for correcting programming failures in an M-bit primary array of programmable fuses. The address of the failed fuse is stored in a secondary fuse array. Correction logic coupled to the primary and secondary arrays propagates the programming states of the good fuses, and corrects the programming state of the failed fuse, if any. The correction logic preferably comprises a decoder coupled to the secondary array which produces a one-hot M-bit word representing the failed fuse, and combinatorial logic arranged to receive the programming states of the primary array fuses and the one-hot M-bit word at respective inputs and to produce the correction logic output. Multiple failures can be accommodated using multiple secondary arrays, each storing the address of a respective failed fuse, or a tertiary array which stores the address of a failed fuse in either the primary or secondary arrays.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.