IC layout pattern matching and classification system and method
US8363922B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 12, 2009 |
| Grant date | Jan 29, 2013 |
| Priority date | — |
| Expiry date | Dec 2, 2031 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2218/16
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system and method for restricting the number of layout patterns by pattern identification, matching and classification, includes decomposing the pattern windows into a low frequency component and a high frequency component using a wavelet analysis for an integrated circuit layout having a plurality of pattern windows. Using the low frequency component as an approximation, a plurality of moments is computed for each pattern window. The pattern windows are classified using a distance computation for respective moments of the pattern windows by comparing the distance computation to an error value to determine similarities between the pattern windows.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.