PLL calibration
US8364098B2 · kind B2 · utility
15Cited by
4References
37Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Apr 30, 2010 |
| Grant date | Jan 29, 2013 |
| Priority date | — |
| Expiry date | Apr 27, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03C3/0991
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A method for applying a modulation signal to a phase locked loop comprises filtering the modulation signal to provide a low frequency component and a high frequency for application to respectively the feedback and feedforward paths of a phase locked loop. The high frequency component is scaled by a gain factor before being applied to the feedforward path. The low frequency component is also scaled by a gain factor and applied to the feedforward path. The energy in a common low frequency range of the modulation signal and of the loop error signal is estimated, and the gain factors are modified dependent on the measured energy.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.