Memory-based FFT/IFFT processor and design method for general sized memory-based FFT processor
US8364736B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 1, 2008 |
| Grant date | Jan 29, 2013 |
| Priority date | — |
| Expiry date | Nov 27, 2031 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F17/142
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
For a large size FFT computation, this invention decomposes it into several smaller sizes FFT by decomposition equation and then transform the original index from one dimension into multi-dimension vector. By controlling the index vector, this invention could distribute the input data into different memory banks such that both the in-place policy for computation and the multi-bank memory for high-radix structure could be supported simultaneously without memory conflict. Besides, in order to keep memory conflict-free when the in-place policy is also adopted for I/O data, this invention reverses the decompose order of FFT to satisfy the vector reverse behavior. This invention can minimize the area and reduce the necessary clock rate effectively for general sized memory-based FFT processor design.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.