Data processing apparatus address range dependent parallelization of instructions
US8364935B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 1, 2003 |
| Grant date | Jan 29, 2013 |
| Priority date | — |
| Expiry date | Sep 25, 2027 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3853
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A data processing apparatus has an instruction memory system arranged to output an instruction word addressed by an instruction address. An instruction execution unit, processes a plurality of instructions from the instruction word in parallel. A detection unit, detects in which of a plurality of ranges the instruction address lies. The detection unit is coupled to the instruction execution unit and/or the instruction memory system, to control a way in which the instruction execution unit parallelizes processing of the instructions from the instruction word, dependent on a detected range. In an embodiment the instruction execution unit and/or the instruction memory system adjusts a width of the instruction word that determines a number of instructions from the instruction word that is processed in parallel, dependent on the detected range.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.