Processor employing split scheduler in which near, low latency operation dependencies are tracked separate from other operation dependencies
US8364936B2 · kind B2 · utility
4Cited by
7References
22Claims
0Family size
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Key dates
| Filing date | Jul 25, 2012 |
| Grant date | Jan 29, 2013 |
| Priority date | — |
| Expiry date | Jul 25, 2032 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3858
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In an embodiment, a scheduler implements a first dependency array that tracks dependencies on instruction operations (ops) within a distance N of a given op and which are short execution latency ops. Other dependencies are tracked in a second dependency array. The first dependency array may evaluate quickly, to support back-to-back issuance of short execution latency ops and their dependent ops. The second array may evaluate more slowly than the first dependency array.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.