Selective power reduction of memory hardware
US8364995B2 · kind B2 · utility
2Cited by
27References
17Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Apr 30, 2012 |
| Grant date | Jan 29, 2013 |
| Priority date | — |
| Expiry date | Apr 30, 2032 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Managing delivery of power to one or more hardware memory devices in a computer system. The computer system is configured with a processor and at least two hardware memory devices. A temperature monitor tool is employed to monitor the hardware memory devices. Management of an addressable subset of the hardware memory devices is employed in response to the monitored temperature reading.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.