Method and apparatus for adaptive power management of memory subsystem
US8365001B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Mar 2, 2009 |
| Grant date | Jan 29, 2013 |
| Priority date | — |
| Expiry date | Mar 7, 2030 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D30/50
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and apparatus are disclosed for performing adaptive memory power management in a system employing a CPU and a memory subsystem. A CPU throttle control (THR) module generates a CPU throttle control signal indicating when the CPU is idle. A memory controller (MC) module generates memory power management signals based on at least one of the CPU throttle control signal, memory read/write signals, memory access break events, and bus master access requests. Certain portions of the memory subsystem are powered down in response to the memory power management signals. Memory power management is performed on a time segment by time segment basis to achieve efficient power management of the memory subsystem during CPU run time.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.