High integrity data bus fault detection using multiple signal components
US8365024B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 26, 2010 |
| Grant date | Jan 29, 2013 |
| Priority date | — |
| Expiry date | Apr 7, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L1/244
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Methods and apparatus are provided for verifying the integrity of a signal transmitted across a multiple rail data bus. The method and apparatus provide for independently processing a signal by a first processor and a second processor, the first and second processors being connected in parallel thereby generating a first processed signal and a second processed signal. Each of the processed signals is split into a first component sequence and a second component sequence, the first component sequences being different from the second component sequences. It is then determined that the first component sequences are not identical and that the second component sequences are not identical. If either of the first component sequences is not identical, or if either of the second component sequences is not identical, then an error signal is transmitted to a receiving device via a first or second rail of the bus.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.