Automatic error diagnosis and correction for RTL designs
US8365110B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 27, 2008 |
| Grant date | Jan 29, 2013 |
| Priority date | — |
| Expiry date | Sep 9, 2030 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/30
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A computer executable tool facilitates integrated circuit design and debugging by working directly at the Register Transfer Level, where most design activities take place. The tool determines when an integrated circuit design produces incorrect output responses for a given set of input vectors. The tool accesses the expected responses and returns the signal paths in the integrated circuit that are responsible for the errors along with suggested changes for fixing the errors. The tool may operate at the RTL, which is above the gate-level abstraction which means that the design errors will be much more readily understood to the designer, and may improve scalability and efficiency.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.