Method and system for a secure power management scheme
US8365308B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 9, 2008 |
| Grant date | Jan 29, 2013 |
| Priority date | — |
| Expiry date | Sep 18, 2031 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F21/81
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A security processor integrated within a system may be securely shut down. The security processor may receive shut down requests, and may determine components and/or subsystems that need be shut down during shut down periods. The security processor may determine when each of the relevant components is ready for shut down. Once the relevant components are shut down, the security processor may itself be shut down, wherein the shut down of the security processor may be performed by stopping the clocking of the security processor. A security error monitor may monitor the system during shut down periods, and the security processor may be powered back on when security breaches and/or threats may be detected via the security error monitor. The security error monitor may be enabled to power on the security processor by reactivating the security processor clock, and the security processor may then power on the system.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.