Methods for a gate replacement process
US8367563B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 7, 2009 |
| Grant date | Feb 5, 2013 |
| Priority date | — |
| Expiry date | May 9, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/017
Abstract
A method for fabricating a semiconductor device is disclosed. In one embodiment, the method may include providing a substrate; forming a gate structure including a first dummy gate over the substrate; removing the first dummy gate from the gate structure to form a trench; forming an interfacial layer, high-k dielectric layer, and capping layer to partially fill in the trench; forming a second dummy gate over the capping layer, wherein the second dummy gate fills the trench; and replacing the second dummy gate with a metal gate. In one embodiment, the method may include providing a substrate; forming an interfacial layer over the substrate; forming a high-k dielectric layer over the interfacial layer; forming an etch stop layer over the high-k dielectric layer; forming a capping layer including a low thermal budget silicon over the etch stop layer; forming a dummy gate layer over the capping layer; forming a gate structure; and performing a gate replacement process.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.