Enhancement-mode HFET circuit arrangement having high power and high threshold voltage
US8368121B2 · kind B2 · utility
10Cited by
4References
17Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 21, 2010 |
| Grant date | Feb 5, 2013 |
| Priority date | — |
| Expiry date | Jan 10, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/513
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A circuit includes input drain, source and gate nodes. The circuit also includes a group III nitride enhancement-mode HFET having a source, drain and gate and a voltage shifter having a first terminal connected to the gate of the enhancement mode HFET at a common junction. The circuit also includes a load resistive element connected to the common junction. The drain of the enhancement-mode HFET serves as the input drain node, the source of the enhancement-mode HFET serves as the input source node and a second terminal of the voltage shifter serves as the input gate node.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.