Semidonductor device having stressed metal gate and methods of manufacturing same

US8368149B2 · kind B2 · utility

Assignee

• TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD. · TW

Inventor

• Robert James Pascoe Lander · Leuven, BE

Key dates

• Filing date: Jun 18, 2012
• Grant date: Feb 5, 2013
• Expiry date: Jun 18, 2032

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D30/794

Abstract

The present disclosure provides various embodiments of a semiconductor device and method of fabricating the semiconductor device. An exemplary semiconductor device includes a semiconductor substrate and a gate stack disposed over the semiconductor substrate. The gate stack includes a gate dielectric layer disposed over the semiconductor substrate and a tuned, stressed metal gate layer disposed over the gate dielectric layer. The tuned, stressed metal gate layer includes a stress that distributes strain differently to portions of the semiconductor substrate having different surface characteristics. In an example, the gate stack is disposed over a portion of a fin of the semiconductor substrate, and the fin has a varying thickness, providing a fin with a roughened surface. The tuned, stressed metal gate layer includes a stress that distributes strain differently to portions of the fin having different thicknesses.