Semiconductor integrated circuit device having improved interconnect accuracy near cell boundaries
US8368225B2 · kind B2 · utility
9Cited by
6References
16Claims
0Family size
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Key dates
| Filing date | May 23, 2011 |
| Grant date | Feb 5, 2013 |
| Priority date | — |
| Expiry date | May 23, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D89/10
Abstract
A layout structure of a semiconductor integrated circuit is provided with which narrowing and breaking of metal interconnects near a cell boundary can be prevented without increasing the data amount and processing time for OPC. A cell A and a cell B are adjacent to each other along a cell boundary. The interconnect regions of metal interconnects from which to the cell boundary no other interconnect region exists are placed to be substantially axisymmetric with respect to the cell boundary, while sides of diffusion regions facing the cell boundary are asymmetric with respect to the cell boundary.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.