In-process system level test before surface mount
US8368416B2 · kind B2 · utility
2Cited by
69References
12Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 11, 2007 |
| Grant date | Feb 5, 2013 |
| Priority date | — |
| Expiry date | Jun 14, 2028 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/2894
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
Methods and systems for testing an integrated circuit during an assembly process are described. The integrated circuit is received from inventory. The integrated circuit is placed in a socket on a first circuit board for system-level testing. The system-level testing is performed prior to placement and permanent attachment of the integrated circuit onto a second circuit board. Provided the integrated circuit passes the system-level testing, the placement and permanent attachment of the integrated circuit to the second circuit board is the next step following the system-level testing in the assembly process.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.