Memory elements with voltage overstress protection
US8369175B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 1, 2010 |
| Grant date | Feb 5, 2013 |
| Priority date | — |
| Expiry date | Apr 14, 2031 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C15/04
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Integrated circuits may include memory elements that are provided with voltage overstress protection. One suitable arrangement of a memory cell may include a latch with two cross-coupled inverters. Each of the two cross-coupled inverters may be coupled between first and second power supply lines and may include a transistor with a gate that is connected to a separate power supply line. Another suitable memory cell arrangement may include three cross-coupled circuits. Two of the three circuits may be powered by a first positive power supply line, while the remaining circuit may be powered by a second positive power supply line. These memory cells may be used to provide an elevated positive static control signal and a lowered ground static control signal to a corresponding pass gate. These memory cells may include access transistors and read buffer circuits that are used during read/write operations.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.