Architecture for address mapping of managed non-volatile memory
US8370603B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 6, 2009 |
| Grant date | Feb 5, 2013 |
| Priority date | — |
| Expiry date | Apr 20, 2031 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/7208
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The disclosed architecture uses address mapping to map a block address on a host interface to an internal block address of a non-volatile memory (NVM) device. The block address is mapped to an internal chip select for selecting a Concurrently Addressable Unit (CAU) identified by the block address. The disclosed architecture supports generic NVM commands for read, write, erase and get status operations. The architecture also supports an extended command set for supporting read and write operations that leverage a multiple CAU architecture.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.