Testing of soft error detection logic for programmable logic devices
US8370691B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 18, 2011 |
| Grant date | Feb 5, 2013 |
| Priority date | — |
| Expiry date | Nov 18, 2031 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/0401
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In one embodiment, a programmable logic device (PLD) with configuration memory includes at least one configuration memory cell and soft error detection (SED) logic for checking for errors in data stored by the configuration memory. The SED logic calculates a present data value for the configuration memory for comparison with a pre-calculated data value. A fuse within the PLD is configurable in a first logic state to enable the SED logic to read from the configuration memory cell in calculating the present data value and configurable in a second logic state to prevent the SED logic from reading from the configuration memory cell in calculating the present data value. The SED logic may be tested for correct operation by writing data representing a soft error into the configuration memory cell and enabling the SED logic to read from the configuration memory cell in calculating the present data value.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.