Semiconductor memory apparatus for reducing bus traffic between NAND flash memory device and controller
US8370699B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 17, 2009 |
| Grant date | Feb 5, 2013 |
| Priority date | — |
| Expiry date | Dec 6, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M13/1545
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Provided is a semiconductor memory apparatus that may use an efficient protocol between an NAND flash memory device and a controller to reduce bus traffic. The flash memory device may include a memory cell array and an error correction encoder. The memory cell array may include a plurality of pages. The error correction encoder may generate first parity data based on normal data to be written to the memory cell array, compare the first parity data and second parity data encoded with the normal data stored in the memory cell array, and check an error. The error position detector may detect an error position in response to the error signal transmitted from the error correction encoder. Thus, since the semiconductor memory apparatus may transmit and receives parity data or a syndrome between an NAND flash memory device and the controller by detecting and correcting an error in the same memory chip, bus traffic may be reduced.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.