Soft output viterbi decoder architecture
US8370726B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Jun 17, 2010 |
| Grant date | Feb 5, 2013 |
| Priority date | — |
| Expiry date | Jul 14, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M13/6505
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A soft output Viterbi algorithm (SOVA) decoder arranged to decode symbols received over a transmission channel, the symbols indicating a state transition between two states of a plurality of states that determines a decoded data value, the SOVA decoder comprising a reliability memory unit including at least four stages of logic units, each logic unit including a single buffer and at least four stages including a plurality of full stages comprising a separate logic unit corresponding to each of the plurality of states; and a plurality of compact stages including half or less than half the number of logic units than the number of the plurality of states, each logic unit corresponding to two of the plurality of states.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.