Semiconductor integrated device and manufacturing method for the same
US8372704B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Feb 22, 2011 |
| Grant date | Feb 12, 2013 |
| Priority date | — |
| Expiry date | Feb 22, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/60
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A manufacturing method for a semiconductor integrated device including forming a second impurity layer of a second conductivity type that is higher in impurity concentration than a second well of the second conductivity type on a first impurity layer of a first conductivity type that is higher in impurity concentration than a first well of the first conductivity type, forming the first well of the first conductivity type on the second impurity layer of the second conductivity type on the first impurity layer of the first conductivity type, the first well being supplied with potential from the first impurity layer of the first conductivity type, and forming the second well of the second conductivity type on the second impurity layer of the second conductivity type on the first impurity layer of the first conductivity type, the second well being supplied with potential from the second impurity layer of the second conductivity type.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.