Semiconductor device and manufacturing method thereof
US8373164B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 6, 2009 |
| Grant date | Feb 12, 2013 |
| Priority date | — |
| Expiry date | Nov 12, 2030 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/02631
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A structure by which electric-field concentration which might occur between a source electrode and a drain electrode in a bottom-gate thin film transistor is relaxed and deterioration of the switching characteristics is suppressed, and a manufacturing method thereof. A bottom-gate thin film transistor in which an oxide semiconductor layer is provided over a source and drain electrodes is manufactured, and angle θ1 of the side surface of the source electrode which is in contact with the oxide semiconductor layer and angle θ2 of the side surface of the drain electrode which is in contact with the oxide semiconductor layer are each set to be greater than or equal to 20° and less than 90°, so that the distance from the top edge to the bottom edge in the side surface of each electrode is increased.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.