Semiconductor device and method of manufacturing the same
US8373216B2 · kind B2 · utility
6Cited by
6References
17Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 27, 2010 |
| Grant date | Feb 12, 2013 |
| Priority date | — |
| Expiry date | Dec 25, 2030 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/0174
Abstract
Technique of improving a manufacturing yield of a semiconductor device including a non-volatile memory cell in a split-gate structure is provided. A select gate electrode of a CG shunt portion is formed so that a second height d2 from the main surface of the semiconductor substrate of the select gate electrode of the CG shunt portion positioned in the feeding region is lower than a first height d1 of the select gate electrode from the main surface of the semiconductor substrate in a memory cell forming region.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.