Alignment mark, method of manufacturing semiconductor device, and mask set
US8373288B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Mar 18, 2010 |
| Grant date | Feb 12, 2013 |
| Priority date | — |
| Expiry date | Feb 9, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B63/84
- WIPO fieldOptics
- WIPO sectorInstruments
Abstract
An alignment mark formed by using a first mask used in forming a same memory cell pattern on a substrate and formed together with the memory cell pattern includes: a first pattern for position detection used for alignment in forming a first wiring pattern; and a first irregular reflection prevention mark that suppresses, when a position detection signal is irradiated as alignment in forming a second wiring pattern further on an upper layer side than the first wiring pattern, irregular reflection of a position detection signal from a second pattern for position detection formed further in a lower layer than the first pattern for position detection.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.