Power stage
US8373454B2 · kind B2 · utility
1Cited by
39References
10Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jul 1, 2010 |
| Grant date | Feb 12, 2013 |
| Priority date | — |
| Expiry date | Nov 14, 2030 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/018528
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An power stage has a differential output stage 2 driven by one or more buffer stages 4. The buffer stages 4 are implemented as high and low side buffers 12,14, each of which is itself a differential buffer implemented using transistors formed in an isolated-well technology such as triple-well CMOS.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.