Electronic device and method for phase locked loop
US8373465B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 17, 2011 |
| Grant date | Feb 12, 2013 |
| Priority date | — |
| Expiry date | Nov 17, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/102
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A phase locked loop (PLL) is provided. The PLL includes a control stage comprising N storage elements each having an output coupled to the output of the control stage. The N storage elements being coupled in a chain, and each storage element being configurable in an analog mode, where a stored signal at the storage node of the storage element is changed continuously in response to the output signal of a charge pump. Each storage element is configurable in a digital mode in which the stored value is one value out of a predetermined set of values, and the storage element can assume the analog mode if a preceding storage element and a subsequent storage element are in the digital mode and have different values of the stored signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.