Patent · US Active

Digital PLL with automatic clock alignment

US8373472B2 · kind B2 · utility

6Cited by

2References

20Claims

0Family size

Assignee

Intel Mobile Communications GmbH · DE

Inventors

Edwin Thaller · Faak am See, AT
Stefano Marsili · Faak am See, AT
Giuseppe Li Puma · Bochum, DE

Key dates

Filing date	Jun 20, 2011
Grant date	Feb 12, 2013
Priority date	—
Expiry date	Jul 1, 2031

Classification

Technology area (CPC H)Electricity
CPC primaryH03L7/183
WIPO fieldBasic communication processes
WIPO sectorElectrical engineering

Abstract

One embodiment of the present invention relates to a digital phase locked loop (ADPLL) configured to generate a plurality of time-aligned output clock signals having different frequency values. The ADPLL comprises a digital controlled oscillator configured to generate a variable clock signal that is separated into two signal paths operating according to two separate clock domains. A first signal path is configured to generate a feedback signal that synchronizes the variable clock signal with a reference signal. A second signal path comprises a clock divider circuit configured to synchronously divide the variable clock signal to automatically generate a plurality of time-aligned output clock signals having different frequencies. A clock aligner monitors a phase difference between the variable clock signal and one of the plurality of time-aligned output clock signals and generates a control signal that causes a programmable delay line to automatically time-align the output clock signals with the variable clock signal.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.